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Looking forward to cooperating with you
1. Perform DFT design and verification tasks for SoC including SCAN insertion, MBIST, functional test logic etc..
2. support DFT related timing constraints and work with physical design team
3. Generate and verify DFT ATPG and functional patterns
4. Other tasks assigned by customer's manager
- Bachelor's or Matser's Degree in EE, MS preferred., with minimal 3 years working experience on DFT
- familiar with DFT tools like TestKompress, FastScan, Tetra max ,MBISTarchitect, BSDarchitect etc..
- Should have strong problem solving skills - Good English hearing, speaking, reading and writing capabilities
- Good team working spirit
1. Design and development of windows driver;
2. Develop the driver of pcle interface card based on KMDF, and carry out version adaptation and transplantation;
3. Windows Desktop C + + client development.
1. Computer related major, bachelor degree or above;
2. More than two years of experience in Windows Driver Design and R & D, proficient in using Windows Driver Kit to customize and modify the driver;
3. Be proficient in C / C + +, have certain reverse analysis ability, strong learning ability and strong research ability;
4. Deeply understand the operation mechanism of windows kernel (file system, disk, memory, process / thread, etc.);
5. Strong sense of responsibility and team work;
6. Work experience in safety related field is preferred;
7. Studied various underlying technologies, such as anti rootkit, hook of core API, etc.
1. Responsible for the development and debugging of the underlying drivers in Linux and windows environment;
2. Specifically undertake the design, coding and debugging of product driving function module;
3. Linux system kernel transplantation, cutting, code performance optimization;
4. Writing of design documents in the process of system development;
5. Carry out product verification, test, fault location and repair together with testing, hardware and other departments;
6. Optimize system performance and power consumption.
1. Bachelor degree or above in computer, electronics, automation and other related majors, proficient in C / C + +;
2. More than two years of experience in kernel clipping and driver software development based on Linux, with FPGA SoC development experience is preferred;
3. Familiar with interrupt, DMA, process scheduling, file system and other operation mechanisms;
4. Familiar with PCIe interface protocol and technical details, SR-IOV development experience is preferred;
5. Have excellent team spirit, dare to undertake and break through.
1. Participate in FPGA logic design to ensure progress;
2. Participate in the overall scheme design of the system;
3. Support software personnel to design corresponding software and communicate with software personnel for collaborative development;
1. More than 6 years of logic design experience;
2. Be familiar with PCIe protocol, and have done the logic design of PCIe board project;
3. It is better to be familiar with Xilinx FPGA, and have done PCIe DMA related projects;
4. It is better to be familiar with board design.
1. Responsible for chip top level or IP integration verification;
2. Work with the designer to develop the verification specification and test plan, and build the verification platform based on UVM;
3. Execute the verification plan, write test cases, carry out recursive testing, and complete the debugging and repair of problems;
4. Responsible for coverage convergence, and design and write test cases to complete cross check before signoff;
5. Carry out gate level function and timing simulation;
6. Provide support for the chip's bring up.
1. 4-6 years IC Verification experience, major in microelectronics, computer, communication, etc., master degree or above;
2. Familiar with IC verification process, rich experience in IP / SoC verification and successful streamer;
3. Familiar with system Verilog and UVM verification methodology;
4. Be familiar with Axi / APB / AHB and other bus protocols;
5. Familiar with clock, reset and low power consumption verification;
6. Familiar with gate level simulation;
7. Be able to identify project risk points, have team spirit, clear thinking, love to study hard, and have the ability to resist pressure.
Address：S1601-S1605, 16 / F, building C, No. 2, South Road of Science Academy, Haidian District, Beijing
Work with Frond-End design team and Physical design team for large scale ASIC chip physical implementation ( Hierarchical Design ). Include top level physical partition , block sizing and shaping , block port assignment, power planning , top/block level P&R implementation .
Work for project high quality and on time delivery.
1. Responsible for Verilog to GDS implementation , power signoff ，area Evaluation ，Timing closure ，STA，Physical verification
2. Experienced in EDA tools (e.g. Synopsys ,Candence , Mentor etc)
3. Critical issue resolve on top congestion or timing issues.
4. Better be expert on one or more aspect like : clock tree synthesis /power/physical verification.
Skills and Knowledge:
1. Good knowledge for synthesis , floorplan , place-and-route , timing closure , DFM , DFT， power analysis, Signal integrity analysis , Hierarchical flow
2. Good at using script processing.(TCL、Perl……)
3. Project tapeout experience is needed
4. 28nm and beyond (advanced node) tapeout experience is a good plus.
5. Strong verbal communication and interpersonal skills to work closely with a variety of individual
6. Team work spirit
Education and Experience
MSEE with 3+ years or Bachelor with 5+ of industrial experience of deep submicron digital ASIC design.
1. Participate in the logic design of Serica chip and cooperate with SOC integration and verification team;
2. The design and implementation of digital chip logic;
1. Major in computer or electronics, master degree or above.
2. Familiar with the processor architecture, with experience in cache, MMU, DMA design is preferred.
3. Familiar with bus protocol, such as AMBA ace, Axi, APB, etc.
4. Have a solid foundation in logic design, understand low-power logic design technology and testability design.
5. Be familiar with the basic verification process, work with the verification team to develop the verification plan and complete the verification convergence.
6. Be familiar with the front-end design process, the use of common front-end EDA tools, and the mainstream tools of Synopsys and cadence. Complete design timing convergence and power consumption evaluation with other teams.
7. 5-10 times of advanced process wafer experience below 28nm.